Makefiles are used to help decide which parts of a large program need to be recompiled. In the vast majority of cases, C or C++ files are compiled. Other languages typically have their own tools that serve a similar purpose as Make. Make can also be used beyond compilation too, when you need a series of instructions to run depending on what files have changed. This tutorial will focus on the C/C++ compilation use case. If any file's dependencies changes, then the file will get recompiled: Here's an example dependency graph that you might build with Make. Popular C/C++ alternative build systems are SCons, CMake, Bazel, and Ninja. Some code editors like Microsoft Visual Studio have their own built in build tools. For Java, there's Ant, Maven, and Gradle. Other languages like Go and Rust have their own build tools. Interpreted languages like Python, Ruby, and Javascript don't require an analogue to Makefiles. The goal of Makefiles is to compile whatever files need to be compiled, based on what files have changed. But when files in interpreted languages change, nothing needs to get recompiled. When the program runs, the most recent version of the file is used. There are a variety of implementations of Make, but most of this guide will work on whatever version you're using. However, it's specifically written for GNU Make, which is the standard implementation on Linux and MacOS. To run these examples, you'll need a terminal and "make" installed.Īll the examples work for Make versions 3 and 4, which are nearly equivalent other than some esoteric differences. Let's start with the simplest of Makefiles: hello: For each example, put the contents in a file called Makefile, and in that directory run the command make. Here is the output of running the above example: $ make Note: Makefiles must be indented using TABs and not spaces or make will fail. The targets are file names, separated by spaces.Ī rule generally looks like this: targets: prerequisites That's it! If you're a bit confused, here's a video that goes through these steps, along with describing the basic structure of Makefiles.Ī Makefile consists of a set of rules.The commands are a series of steps typically used to make the target(s).These need to start with a tab character, not spaces. The prerequisites are also file names, separated by spaces.Let's start with a hello world example: hello:Įcho "This line will always print, because the file hello does not exist." These files need to exist before the commands for the target are run. As long as the hello file does not exist, the commands will run. If hello does exist, no commands will run. It's important to realize that I'm talking about hello as both a target and a file. That's because the two are directly tied together. Typically, when a target is run (aka when the commands of a target are run), the commands will create a file with the same name as the target. In this case, the hello target does not create the hello file. But before we do, make a file called blah.c that has the following contents: // blah.c int main () or $() x := dude Let's create a more typical Makefile - one that compiles a single C file. Making multiple targets and you want all of them to run? Make an all target. Since this is the first rule listed, it will run by default if make is called without specifying a target. When there are multiple targets for a rule, the commands will be run for each target.
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